`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:19:03 11/11/2014
// Design Name:   Main
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/uart-arquitectura-2014/Main-Test.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module MainGuionTest;

	// Inputs
	reg clk;
	reg reset;
	reg rx;

	// Outputs
	wire tx;

	// Instantiate the Unit Under Test (UUT)
	Main uut (
		.clk(clk), 
		.reset(reset), 
		.rx(rx), 
		.tx(tx)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		rx = 1;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 0;  
		// Add stimulus here
		rx = 0; //bit Start
		#2600;
		rx = 1;
		#5200;
		rx = 0;
		#5200;
		rx = 1;
		#5200;
		rx = 0;
		#5200;
		rx = 1;
		#5200;
		rx = 0;
		#5200;
		rx = 1;
		#5200;
		rx = 0;
		#5200;
		rx = 1; // Bit de fin
		#5000;
		
		

	end
 
 always begin
 #1; clk = ~clk;
 end
 
endmodule

